IJITCS Vol. 17, No. 2, 8 Apr. 2025
Cover page and Table of Contents: PDF (size: 400KB)
PDF (400KB), PP.1-9
A rapid and energy-efficient floating point unit is constantly required for significant applications such as digital signal processing, image processing, real-time data processing, and multimedia applications. This project suggests using a single-precision Floating Point Multiplier engine to speed FPGA applications. The engine has a modified approach for virtual zeropadding to conserve memory space, and it also includes customizable settings for filter and picture size. To improve the suggested multiplier design, a low power multiplier with lower dynamic power, notably while acting on pixels, has been presented, as well as a quicker increment by one circuit based on gates. Finally, the project displays the post-synthesis power dissipation, area estimation, and picture quality comparison achieved from the suggested architecture's RTL simulation.
Thangamani C, Poovarasan R, "An Efficient Floating-Point Multiplier For Low Power Single Precision FPGA Implementation", International Journal of Information Technology and Computer Science(IJITCS), Vol.17, No.2, pp.1-9, 2025. DOI:ijitcs/10.96856/2025
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